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Microprocessors And Microcontrollers — Part 2 MCQs with Explanations

Practice high-yield Electronics & Communications Engineering MCQs on Microprocessors And Microcontrollers — Part 2 with worked academic solutions for FPSC, PPSC, PTA, PAEC, NTS.

Questions
40
Difficulty Level
Exam-Level
Target Exams
FPSC, PPSC, PTA...
Estimated Time
48 mins
Exam-Level FPSC PPSC PTA PAEC NTS
Verified for Commission Syllabus • Oct 14, 2026
40

Verified Practice Questions

Interactive test mode with detailed academic worked solutions

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Question 1 of 40
★ FPSC ★ PPSC

IC 7485 cannot be cascadeD.

Question 2 of 40
★ FPSC ★ PPSC

‘Burst refresh’ in DRAM is also called

Question 3 of 40
★ FPSC ★ PPSC

When .9432 E – 4 is subtracted from .5452 E – 3 in normalized floating point mode

Question 4 of 40
★ FPSC ★ PPSC

In 8085, the pins for SID and SOD are

Question 5 of 40
★ FPSC ★ PPSC

An Input/Output processor controls the flow of information between

Question 6 of 40
★ FPSC ★ PPSC

MS Access is a DBMS software.

Question 7 of 40
★ FPSC ★ PPSC

Which of the following is not a general purpose peripheral?

Question 8 of 40
★ FPSC ★ PPSC

In Fortran 77 a variable name can contain special characters.

Question 9 of 40
★ FPSC ★ PPSC

It is possible to copy a file in the same directory.

Question 10 of 40
★ FPSC ★ PPSC

What is the addressing mode used in instruction MOV M, C?

Question 11 of 40
★ FPSC ★ PPSC

In microprocessor's stack, what does the operation push cx means?

Question 12 of 40
★ FPSC ★ PPSC

How many bits are used as conditional flags in the flag register of 8086?

Question 13 of 40
★ FPSC ★ PPSC

If B 7 and B 6 bits of mode register in 8237 are set to 11, which mode of operation is selected?

Question 14 of 40
★ FPSC ★ PPSC

The address bus of Intel 8085 is 16-bit wide and hence the memory which can be accessed by this address bus is

Question 15 of 40
★ FPSC ★ PPSC

What is the size(in bits) of the stack pointer in 8085?

Question 16 of 40
★ FPSC ★ PPSC

Interrupt latency is the time elapsed between:

Question 17 of 40
★ FPSC ★ PPSC

1. Program Counter (PC) Pushed to Stack 2. Generate LCALL to ISR 3. Complete Execution of instruction in progress 4. Clear the interrupt flag 5. Set interrupt in progress Correct order of execution of action taken by 8051 micro-controllers when an interrupt occurs:

Question 18 of 40
★ FPSC ★ PPSC

Which of the 8086 instruction can be used to fetch a string of 16-bit word stored in memory, automatically incrementing the memory pointer?

Question 19 of 40
★ FPSC ★ PPSC

Which of the following are two most commonly used industry standards for interchip serial communications?

Question 20 of 40
★ FPSC ★ PPSC

Consider the following instruction of 8085 µP. 1. MOV M, A 2. ADD C 3. MVI A, FF 4. CMP M Which of these cause change in the status of flag(s)?

Question 21 of 40
★ FPSC ★ PPSC

What is the total external data memory that can be interfaced to the 8051?

Question 22 of 40
★ FPSC ★ PPSC

Considering figure 1, if SI = 1000H, the content of register AH after the instruction MOV AH, [SI] of 8086 µp will be

Question 23 of 40
★ FPSC ★ PPSC

In a computer, set of electrical paths which is used to transfer data is called

Question 24 of 40
★ FPSC ★ PPSC

Address bus of 8086 contains

Question 25 of 40
★ FPSC ★ PPSC

An 8-bit microprocessor has the typical two way connected buffered lines which are called:

Question 26 of 40
★ FPSC ★ PPSC

Consider the following statements: The 8259A Programmable Interrupt Controller can 1. manage eight interrupts 2. vector an interrupt request anywhere in the memory map 3. have 8-bit or 16-bit interval between interrupt vector locations 4. be initialized with operational command words Which of the above statements are correct?

Question 27 of 40
★ FPSC ★ PPSC

A controller that takes control of the buses and transfers data directly between source and destination bypassing the microprocessor is known as

Question 28 of 40
★ FPSC ★ PPSC

In a 8051 microcontroller, PCON register controls the baud rate in: 1. Synchronous transmission 2. Asynchronous transmission

Question 29 of 40
★ FPSC ★ PPSC

In 8051 family instructions, which one of the following option is true?

Question 30 of 40
★ FPSC ★ PPSC

If the operating frequency of an 8086 microprocessor is 10 MHz and, if for the given instruction, the machine cycle consists of 4 T-states, what will be the time taken by the machine cycle to complete the execution of that machine cycle to complete the execution of that same instruction when three wait states are inserted?

Question 31 of 40
★ FPSC ★ PPSC

A stake machine pushes operands on a stack and evaluates binary operators by a pcs (i.e pop/compute/store) where the top two operands are popped computation is performed and the result is pushed onto stack. Evaluation of an expression (x*y)+ (u*v) by Reverse Polish notation in a stack machine needs

Question 32 of 40
★ FPSC ★ PPSC

The first machine cycle of an instruction is always

Question 33 of 40
★ FPSC ★ PPSC

A CDMA system requires $$\frac{{{{\text{E}}_{\text{b}}}}}{{{{\text{I}}_0}}}$$ of 10 dB. Each of the transmitters in the network transmits data at the rate of 1 Kbps with a PN chip rate of 1 Mbps. The maximum number of such users that the network can support is:

Question 34 of 40
★ FPSC ★ PPSC

If instruction RST 5 is written in a program the problem will jump to location

Question 35 of 40
★ FPSC ★ PPSC

In case the code is position dependent, the most suitable addressing mode is

Question 36 of 40
★ FPSC ★ PPSC

The number of pins in microprocessor 8086 is

Question 37 of 40
★ FPSC ★ PPSC

Which one of the following pairs of 8086 microprocessor's interrupt is not correctly matched?

Question 38 of 40
★ FPSC ★ PPSC

Which instruction of 8051 microcontroller is used for reading data from code memory?

Question 39 of 40
★ FPSC ★ PPSC

The following instructions have been executed by an 8085 microprocessor ADDRESS (HEX) INSTRUCTION 6010 LXI H, 8A79H 6013 MOV A, L 6014 ADD H 6015 DAA 6016 MOV H, A 6017 PCHL From which address will the next instruction be fetched?

Question 40 of 40
★ FPSC ★ PPSC

Which of the following interrupts is unmaskable interrupts

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💡 Examiner's Advisory for Electronics & Communications Engineering

In competitive commission exams (FPSC, PPSC, KPPSC, SPSC, CSS, PMS), questions are frequently phrased with distractor options designed to catch rote learners. Whenever you answer an MCQ, read the Detailed Academic Explanation and Conceptual Anchor to understand why the remaining options are incorrect.

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