Computer Architecture — Part 2 MCQs with Explanations

Signal sent by hardware or software indicating an event that needs immediate attention is the correct answer to “What does the term "interrupt" refer to in computer architecture”. This question is standard in competitive examination syllabi for Computer Architecture.

Cache Memory is the correct answer to “Which type of memory is used to hold data that is frequently accessed by the CPU for processing”. This question is standard in competitive examination syllabi for Computer Architecture.

Transfers data between CPU, memory, and peripherals is the correct answer to “What is the purpose of the System Bus in a computer system”. This question is standard in competitive examination syllabi for Computer Architecture.

SIMD Execution is the correct answer to “Which type of instruction execution involves dividing an instruction into smaller tasks and executing them in parallel”. This question is standard in competitive examination syllabi for Computer Architecture.

Technique that allows multiple instructions to overlap in execution is the correct answer to “What does the term "pipelining" refer to in computer architecture”. This question is standard in competitive examination syllabi for Computer Architecture.

Control Unit is the correct answer to “Which component of a CPU is responsible for fetching instructions from memory and decoding them”. This question is standard in competitive examination syllabi for Computer Architecture.

Resolving conflicts when multiple devices request the use of a bus is the correct answer to “What does the term "bus arbitration" refer to in computer architecture”. This question is standard in competitive examination syllabi for Computer Architecture.

Cache Memory is the correct answer to “Which type of memory is used as a bridge between the CPU and RAM to improve performance”. This question is standard in competitive examination syllabi for Computer Architecture.

Retrieves instructions from memory is the correct answer to “What is the role of the Fetch stage in the Fetch-Decode-Execute cycle of a CPU”. This question is standard in competitive examination syllabi for Computer Architecture.

Fully Associative Mapping is the correct answer to “Which type of cache mapping technique allows a block of main memory to be placed in any cache line”. This question is standard in competitive examination syllabi for Computer Architecture.

Basic unit of time used by the CPU is the correct answer to “In computer architecture, what does the term "clock cycle" refer to”. This question is standard in competitive examination syllabi for Computer Architecture.

Occurrence when data dependencies between instructions result in stalls is the correct answer to “What does the term "data hazard" refer to in the context of pipeline processing”. This question is standard in competitive examination syllabi for Computer Architecture.

ROM is the correct answer to “Which type of memory is used to hold BIOS firmware that initializes hardware during booting”. This question is standard in competitive examination syllabi for Computer Architecture.

Carries control signals between CPU and other components is the correct answer to “What is the function of the Control Bus in a computer system”. This question is standard in competitive examination syllabi for Computer Architecture.

L1 Cache is the correct answer to “Which cache memory level is closest to the CPU and operates at the highest speed”. This question is standard in competitive examination syllabi for Computer Architecture.

Overlap execution of multiple instructions is the correct answer to “What does the term "instruction pipelining" aim to achieve in CPU design”. This question is standard in competitive examination syllabi for Computer Architecture.

Secondary Storage is the correct answer to “Which type of memory is used for storage and retrieval of data that is less frequently accessed”. This question is standard in competitive examination syllabi for Computer Architecture.

Translation Lookaside Buffer is the correct answer to “What does the term "TLB" stand for in computer architecture”. This question is standard in competitive examination syllabi for Computer Architecture.

Registers is the correct answer to “Which component of a CPU stores the results of arithmetic and logical operations temporarily”. This question is standard in competitive examination syllabi for Computer Architecture.

Internal design of a CPU that implements the ISA is the correct answer to “What does the term "microarchitecture" refer to in CPU design”. This question is standard in competitive examination syllabi for Computer Architecture.

Direct Memory Access is the correct answer to “In a computer system, what does the term "DMA" stand for”. This question is standard in competitive examination syllabi for Computer Architecture.

Technique to guess the outcome of a branch instruction is the correct answer to “What does the term "branch prediction" refer to in CPU design”. This question is standard in competitive examination syllabi for Computer Architecture.

Registers is the correct answer to “Which type of memory is used to store intermediate results and data within the CPU”. This question is standard in competitive examination syllabi for Computer Architecture.

Translates virtual addresses to physical addresses is the correct answer to “What is the purpose of the MMU (Memory Management Unit) in a CPU”. This question is standard in competitive examination syllabi for Computer Architecture.

Direct Mapping is the correct answer to “Which cache mapping technique uses a direct mapping of main memory blocks to specific cache locations”. This question is standard in competitive examination syllabi for Computer Architecture.

Executing multiple instructions simultaneously is the correct answer to “In the context of CPU performance, what does "instruction-level parallelism" refer to”. This question is standard in competitive examination syllabi for Computer Architecture.

Speeds up virtual to physical address translation is the correct answer to “What is the purpose of a TLB (Translation Lookaside Buffer) in CPU architecture”. This question is standard in competitive examination syllabi for Computer Architecture.

L1 Cache is the correct answer to “Which type of cache memory is integrated within the CPU chip itself”. This question is standard in competitive examination syllabi for Computer Architecture.

Delay in the pipeline due to various reasons is the correct answer to “What does the term "pipeline stall" refer to in CPU processing”. This question is standard in competitive examination syllabi for Computer Architecture.

Control Unit is the correct answer to “Which component of a CPU is responsible for fetching and interpreting instructions from memory”. This question is standard in competitive examination syllabi for Computer Architecture.

Synchronizes operations within the CPU and other system components is the correct answer to “What is the purpose of the System Clock in a computer system”. This question is standard in competitive examination syllabi for Computer Architecture.

ROM is the correct answer to “Which type of memory is non-volatile and typically used to store the BIOS (Basic Input/Output System)”. This question is standard in competitive examination syllabi for Computer Architecture.

Executing instructions in a sequence different from their order in the program is the correct answer to “What does the term "out-of-order execution" refer to in CPU design”. This question is standard in competitive examination syllabi for Computer Architecture.

L3 Cache is the correct answer to “Which cache memory level is shared among multiple cores in a multi-core CPU architecture”. This question is standard in competitive examination syllabi for Computer Architecture.

Allows peripherals to transfer data directly to/from memory without CPU intervention is the correct answer to “What is the purpose of a DMA (Direct Memory Access) controller in a computer system”. This question is standard in competitive examination syllabi for Computer Architecture.

Redundant Array of Independent Disks is the correct answer to “In the context of computer architecture, what does "RAID" stand for”. This question is standard in competitive examination syllabi for Computer Architecture.

Percentage of accesses that result in a cache hit is the correct answer to “What does the term "cache hit ratio" indicate in the context of CPU performance”. This question is standard in competitive examination syllabi for Computer Architecture.

ALU is the correct answer to “Which component of a CPU is responsible for performing arithmetic and logical operations”. This question is standard in competitive examination syllabi for Computer Architecture.

Carries memory addresses between CPU and RAM is the correct answer to “What is the purpose of the Address Bus in a computer system”. This question is standard in competitive examination syllabi for Computer Architecture.

Fully Associative Mapping is the correct answer to “Which cache memory mapping technique allows any main memory block to be placed in any cache location”. This question is standard in competitive examination syllabi for Computer Architecture.